1. Field of the Invention
The present invention relates generally to cascode transistor arrangements.
2. Description of the Related Art
For metal-oxide-semiconductor transistors, a cascode arrangement often couples a common-gate cascode transistor to the drain of a second transistor. The cascode transistor provides a substantially enhanced output impedance. Other cascode transistors can be added to further enhance the output impedance. Although various networks have been proposed for biasing cascode arrangements, they have generally failed to accurately bias the second transistor at a desired point in its saturation region and maintain that point over variations in operating conditions (e.g., process, supply and temperature).